Home/ Questions/Q 8299711
In Process

The Archive Base Latest Questions

Editorial Team
  • 0
Asked: 2026-06-08T16:15:37+00:00

From the Intel x86 System Programming Guide : PGE Page Global Enable (bit 7

  • 0

From the Intel x86 System Programming Guide :

PGE Page Global Enable (bit 7 of CR4) — (Introduced in the P6 family processors.)
Enables the global page feature when set; disables the global page feature when clear. The global page feature allows frequently used or shared pages to be marked as global to all users (done with the global flag, bit 8, in a page-directory or page-table entry). Global pages are not flushed from the translation-lookaside buffer (TLB) on a task switch or a write to register CR3.

Is there any equivalent feature on PowerPC e500 core family ?

Thanks,
Telenn

Share

Leave an answer

You must login to add an answer.

Need An Account,

1 Answer

  1. Editorial Team

    Looking at the e500 Core Reference Manual (downloadable from freescale.com) I found that the MAS[0-4] registers do roughly what you need (section 2.12). This is part of the Freescale Book E implementation, so further details can also be found on freescale.com.

    • 0