Question

I am debugging a piece of software on an ARM chip via GDB. After loading the program (and before running it), when I do info registers I get:

(gdb) info registers
r0             0x0      0
r1             0x0      0
r2             0x0      0
r3             0x0      0
r4             0x0      0
r5             0x0      0
r6             0x0      0
r7             0x0      0
r8             0x0      0
r9             0x0      0
r10            0x0      0
r11            0x0      0
r12            0x0      0
sp             0x4770   0x4770
lr             0xffffffff       4294967295
pc             0x8005dc5        0x8005dc5 <Reset_Handler+1>
fps            0x0      0
cpsr           0x20     32

The one register I find worrisome is lr set to 0xffffffff. I am thinking this may be the reason for my crash.

Is it normal to have lr initiated to 0xffffffff?

Answer 1

This looks like a situation where you have the debugger stopping execution very shortly after reset (I’m basing this on your description and the symbol name associated with the PC value). If so, don’t worry about the inital state of lr – just don’t use it until you’ve initialized it (which probably wouln’t make much sense anyway until it was explicitly set by your assembly code or by the C compiler to handle a function call).

Since another person guessed that you were using a Cortex-M3 processor, here’s some of what the Technical Reference Manual says about the processor’s behavior at reset:

5.9 Resets

The NVIC is reset at the same time as the core and controls the
release of reset into the core. As a result, the behavior of reset is
predictable. Table 5-7 shows the reset behavior. For more information
about resets, see Chapter 6 Clocking and Resets.

Table 5-7 Reset actions

Action                                Description
=================================   ====================================================

NVIC resets, holds core in reset    NVIC clears most of its registers. The processor is 
                                    in Thread mode, priority is privileged, and the stack 
                                    is set to Main.

NVIC releases core from reset       NVIC releases core from reset.

Core sets stack                     Core reads the start SP, SP_main, from vector-table offset 0.

Core sets PC and LR                 Core reads the start PC from vector-table offset. 
                                    LR is set to 0xFFFFFFFF.

Reset routine runs                  NVIC has interrupts disabled, and NMI and Hard Fault 
                                    are not disabled.

So if you’re running an M3, that’s why lr is set to 0xffffffff.

I don’t see any mention of how the other general purpose registers are initialized at reset – I wouldn’t count on them being zero. Initialize them yourself.

If you’re not running an M3, the “What values are in ARM registers after a power-on reset?” note may apply to your device. It says:

Registers R0 – R14 (including banked registers) and SPSR (in all modes) are undefined after reset.

(r14 is lr).