Question

If I run make clean twice the second invocation will build the dependency Makefiles that are scheduled for removal. How can I get Makefile to recognize the files scheduled for removal and skip the recursive call to make for that directory? In other words, only make clean in sub directory if the makefile already exists in each sub directory, on a per sub directory basis. I don’t know the GNU-Make syntax but I’m looking for something like:

Dependencies=[dependency1,dependency2,dependency3,dependency4]
DoNotMake=[bool1,bool2,bool3,bool4]
for all (i < 4): 
    if (! Dependencies(i)/Makefile):
        DoNotMake(i)=true

The current rules for make clean are as follows:

.PHONY: clean
clean:
    $(MAKE) MAKEDEPEND=off SUBDIR_ARGS=clean
    rm -f dependency1/Makefile
    rm -f dependency2/Makefile
    rm -f dependency3/Makefile
    rm -f dependency4/Makefile
    rm -f dependency4/src/config.h.in

Answer 1

I can’t give you a definite answer since there’s still a lot of your makefile that you haven’t posted, but here are some things that we do to solve similar problems.

The make variable MAKECMDGOALS contains the current make target. If you want to avoid doing something when you run make clean, you can do something like this:

ifeq (,$(findstring $(MAKECMDGOALS),clean))
  # Whatever you place here won't be run when you run 'make clean'
endif

You can also add a bit of shell script to only invoke a sub-makefile when it exists:

some_target:
    [ -f $(SUB_FOLDER)/Makefile ] && $(MAKE) -C $(SUB_FOLDER)

If your makefiles are being created implicitly, then these may not work. You may be able to use the --assume-old= option to prevent make from re-building the makefiles (I’ve never tried to use that on a file that doesn’t exist, so YMMV).