Question

My makefile contains the following lines

 11 SRC := $(shell echo src/*.cpp)
 12 SRC += $(shell echo $(TEST_ROOT)/*.cpp)
 13 
 14 OBJECTS = $(SRC:.cpp=.o)

 22 # [debug] target
 23 $(TARGET): $(OBJECTS)
 24   $(CC) $(OBJECTS) -o $(TARGET)
 25 
 26 # [debug] .o
 27 $(OBJECTS): $(SRC)
 28   $(CC) $(CFLAGS) $(DEBUG_FLAGS) -c $(SRC) $(OBJECTS)

Which fails because … well the following evidently is not a way to do it

g++ -pedantic -Wall -Werror -O0 -g -Wno-format -DUSE_MEASURE -c src/Timer.cpp test/TimerTest.cpp src/Timer.o test/TimerTest.o

How should i modify line #28 to produce .o from all my sources please?

Answer 1

This should do the trick:

$(OBJECTS): %.o : %.cpp
    $(CC) $(CFLAGS) $(DEBUG_FLAGS) -c $< $@

This rule will build one object file, and Make will call it once for each object that the other rule needs. You can write a rule that will build all object files in one pass, but there’s no advantage to that.

EDIT:

Suppose SRC is src/foo.cpp src/bar.cpp testroot/baz.cpp,

so OBJECTS is src/foo.o src/bar.o testroot/baz.o

We could have a separate rule for each:

src/foo.o : src/foo.cpp
    ...

src/bar.o : src/bar.cpp
    ...

testroot/baz.o : testroot/baz.cpp
    ...

But that’s redundant (since the commands are very similar) and inconvenient (since we don’t want to add/remove rules whenever we add/remove targets). So we use a pattern rule:

%.o : %.cpp
    ...

Now when Make wants to build src/foo.o, it sees that the target matches the pattern %.o, the stem (corresponding to %) is src/foo, and the corresponding prereq, src/foo.cpp exists, so it uses this rule.

But we have a variable OBJECTS that lists the targets we want to build with this rule, so we can restrict it to a static pattern rule, which looks about the same but has some advantages we need not get into here:

$(OBJECTS) : %.o : %.cpp
    ...

Now for the ... part. The command tells the compiler to scan the prereq (src/foo.cpp) and build the target (src/foo.o), so we must refer to those things in the command. Automatic variables help with that; $@ is the name of the target, and $< is the name of the first (and in this case the only) prerequisite:

$(OBJECTS): %.o : %.cpp
    $(CC) $(CFLAGS) $(DEBUG_FLAGS) -c $< $@