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After dealing with a Pipeline Multiplier and a Signed Adding Accumulator, I was wondering if I could implement a Pipeline Accumulator in VHDL.
Since the Accumulator utilized the Core-Gen I don’t know how to go about this…maybe use registers in place of the accumulator and then keep updating the registers? I’d appreciate any ideas and help on this!
When you instantiate the accumulator in Core-Gen, you can specify the desired latency. The Xilinx tools will insert the appropriate number of registers and optimize the adder logic for you auto-magically.
See the Xilinx data-sheet for their Accumulator function for full usage details.