Question

An interrupt causes the CPU to save the EFLAGS, CS and IP registers onto the “stack” and the iret instruction pops them off it. Where is this stack located? How does the CPU know about it (I assume some register somewhere)? I want the dirty details. I am looking at Unix based systems. Say Linux.

Answer 1

First, check out the Intel manuals for all the specifics:
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html

As to your questions:

Where is the stack located?

On an interrupt, an x86 core loads the stack pointer from the Task-state Segment (TSS). The IDT specifies which TSS to use via a task selector field. In 32-bit mode, the TSS provides 4 stack pointers, one per each protection level. Since the protection level is usually just 0 or 3, only two stacks are relevant. In 64-bit mode, the interrupt descriptor entry can optionally specify an index 0-7 of which stack pointer to use within a given 64-bit TSS. Due to reentrancy problems though, this 64-bit stack selection mechanism is mostly broken and OS’s resort to software switching. Check out the x86 Programmer Reference Volume 3, Figure 7-2.

If the interrupt moves the core to a higher privilege level (numerically lower CPL), then the core pushes the interrupt stack frame onto this new stack, not the current stack of the interrupted process. If the privilege level stays the same, then the core just pushes the interrupt stack frame in place on the current stack.

How does the CPU know about it?

The interrupt descriptor table (IDT) provides a descriptor per each interrupt vector, 0-255. The descriptor entry tells the core which TSS (i.e. stack) to use, whether user-mode can call through the vector, whether interrupt are disable on ISR entry, etc. See PRM Volume 3, chapter 6. So, all interrupt processing is really anchored by the information in the IDT.