Are there any grammars for system Verilog that are open source? I’m looking for System Verilog, not plain Verilog grammars.
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Are there any grammars for system Verilog that are open source? I’m looking for System Verilog, not plain Verilog grammars.
Verilog-Perl is open source and claims to have SystemVerilog support. You could contact the Perl CPAN author to see if it covers the complete grammar (his email address is listed on the CPAN page).