As I understand, the address of code instructions are virtual addresses, but in order to access the various devices (e.g. RAM, Parallel NOR Flash) these virtual addresses need to be translated into physical addresses, this task is done by the MMU. The question is how this translation process behaves on system reset (on power up, I think that there is no entry in the MMU yet), so that the first instruction can be fetched from the Parallel NOR Flash and started executing. May anyone please explain this process (for any CPU architecture ARM, PowerPC, …, I just guess this behavior is generic among architectures).
As I understand, the address of code instructions are virtual addresses, but in order
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At power-up, in effect the MMU will be disabled. That much is generic.
To access NOR flash, there would be a default mapping for (at least) some of the address space. First instruction would be typically fetched from 0xFFFF0000 (ARM) or 0xFFFFFFFC (Power PC) and vicinity. But there are pinstrap options that can affect this. Booting a processor is not really generic.
There are plenty of other options (NAND flash, SPI ROM, MMC) for storing boot code. For general concepts, Hallinan includes a chapter on booting. For details you’d have to look at the technical manual of a specific CPU, e.g. OMAP4 TRM is an example for ARM, then find sections describing boot process.