As the Intel Manual illustrated, both Interrupt Gate and Trap Gate can be used to access a handler routine. And some exceptions even share vector numbers with interrupts. I am wondering when such a shared vector is detected by the CPU, how could CPU know whether it stands for an exception or an interrupt?
I am kind of confused about the logic among the following things:
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the decision of the gate types in the IDT
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the judgement of whether the vector stands for an exception or an interrupt
Which decides which?
I hope I made myself clear…
Update 1
Thanks for nos’ reply. Do you mean I have to tell CPU which vector stands for an Interrupt or Trap? I know that CPU treat EFLAGS[IF] differently with regards to Interrupt and Trap, how does CPU know how to make this decision? Does CPU make decision based on the type fields of the IDT entry corresponding to the vector? Or rather it depends on how the system is wired up and we must set the type of the IDT entry according to that? i.e. Is the type fileds totally an illustration for us or imperative to the CPU?
and a related question: The difference between Call Gate, Interrupt Gate, Trap Gate?
You have to program the CPU as to what is an interrupt gate and what is a trap gate for a given ISR.
This is set by bit 40-43 in an IDT entry. Info here: http://wiki.osdev.org/Interrupt_Descriptor_Table