At some point, a colleague and I grabbed an “example” makefile from the net for building our embedded code for an xmega chip. We’ve found the experience very frustrating. Neither of us are make experts, novice at best. We get by making the occasional tweak/adjustment. We spend hours reading make manuals and throwing darts to try and do more serious changes.
Usually when we build though, we always start with a clean all. Because the auto depend generation doesn’t seem to work reliably and we’ve just learned that it’s safer this way. Since it’s an embedded project, on a small processor, the compile actually flies. It’s done in an eye blink, which leads me to my real question here:
If I’m not using make to do any sort of dependency management and leverage incremental building, is there any real sense in using it instead of a simple shell script?
I’m much more confident writing C code, python, and good ol’ bash scripts. Today’s latest frustration, was trying to move a handful of our source files related to FreeRTOS into a subdirectories. The only real advantage of make for us, is that it is stock installed on OSX, and that vi and QtCreator and XCode have some ability to integrate with our makefile (but I could make a very minimal makefile that bridged here).
This is a question I set to myself a while ago. Personally I use python script to compile my code for AVR (link). I am not a make expert but I do have some experience with it. Still I find it frustrating and for uC needs worthless, unless you are anyway already an expert.
Not that I would encourage anyone to do so, but nothing can stop you from implementing the same dependency checking in Python (Perl, Ruby, Bash…), possibly even much more powerful. I believe it is just a matter of language choice or what you feel comfortable with. make is just a kind of programing language and it might seem quite obscure for beginner.