Consider a VLIW processor with an issue width equal to N: this means that it is able to start N operations simultaneously, so each very long instruction can consist of a maximum of N operations.
Suppose that the VLIW processor load a very long instruction which consists of operations with different latencies: operations belonging to the same very long instruction could end at different times. What happens if an operation finishes its execution before other operations belonging to the same very long instruction? Could a subsequent operation (that is an operation belonging to the next very long instruction) start execution before the remaining operations of the current very long instruction being executed? Or does a very long instruction wait for the completion of all operations belonging to the current very long instruction?
The idea behind VLIW is that the compiler figures out lots of things for the processer to do in parallel and packages them up in bundles called “Very long instruction words”.
Amhdahl’s law tells us the the speedup of a parallel program (eg., the parallel parts of the VLIW instruction) is constrained by the slowest part (e.g, the longest-duration subinstruction).
The simple answer with VLIW and “long latencies” is “don’t mix sub-instructions with different latencies”. The practical answer is the VLIW machines try not to have sub-instructions with different latencies; rather ideally you want “one clock” subinstructions. Typically even memory fetches take only one clock by virtue of being divided into “memory fetch start (here’s an address to fetch)” with the only variable latency subinstruction being “wait for previous fetch to arrive” with the idea being that the compiler generates as much other computation as it can so that the memory fetch latency is comvered by the other instructions.