could L1/L2 cache line each cache multiple copies of the main memory data word?
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could L1/L2 cache line each cache multiple copies of the main memory data word?
It’s possible that the main memory is in a cache more than once. Obviously that’s true and a common occurrence for multiprocessor machines. But even on uni processor machines, it can happen.
Consider a Pentium CPU that has a split L1 instruction/data cache. Instructions only go to the I-cache, data only to the D-cache. Now if the OS allows self modifying code, the same memory could be loaded into both the I- and D-cache, once as data, once as instructions. Now you have that data twice in the L1 cache. Therefore a CPU with such a split cache architecture must employ a cache coherence protocol to avoid race conditions/corruption.