Question

entity Adder4Bit is
Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
       B : in  STD_LOGIC_VECTOR (3 downto 0);
       S : out  STD_LOGIC_VECTOR (3 downto 0);
       COUT : out  STD_LOGIC);
end Adder4Bit;

architecture structure of Adder4Bit is

component FullAdder -- add the fulladder to this architecture
port (
        A       : in std_logic;
        B       : in std_logic;
        CIN : in std_logic;
        SUM : out std_logic;
        COUT    : out std_logic
        );
end component;

signal wires : std_logic_vector(3 downto 1) := "000";       -- Make a signal "wires" with initial value 000

begin

adder0 : FullAdder port map ( A=> A(0), B => B(0), CIN => '0', SUM => S(0), COUT => wires(1)        );
adder1 : FullAdder port map ( A=> A(1), B => B(1), CIN => wires(1), SUM => S(1), COUT => wires(2)   );
adder2 : FullAdder port map ( A=> A(2), B => B(2), CIN => wires(2), SUM => S(2), COUT => wires(3)   );
adder3 : FullAdder port map ( A=> A(3), B => B(3), CIN => wires(3), SUM => S(3), COUT => COUT       );


end structure;

In adder3 at the very bottom, how do the program know what cout belongs to the entity Adder4Bit and what cout belongs to the component FullAdder?
Does it have anything to do with the direction of the arrow?

Thank you very much in advance

Answer 1

Of course, the left side is the name inside the component, and the right side is the name of you vhdl signal.

It’s the same way it knows that the left B is std_logic while the right one is the std_logic_vector.