Question

Firstly, I am a beginner learning Assembly/Machine code, so forgive me if I am asking the obvious.

I was reading some code and came across a snippit where the code puts “1.0” into a floating point coprocessor registers.

The code is

addi       $t5, $0, 1
mtc1       $t5, $f2
cvt.s.w    $f0, $f2       # 1.0 in $f0

My first question is:

Why does it have to put “1” into “$t5” first, before transferring it into a coprocessor? Wouldn’t it be easier to do

addi       $f2, $0, 1

or even

addi       $f2, $0, 1.0

My second question is:

for this line of code

 cvt.s.w    $f0, $f2       # 1.0 in $f0

Is it necessary for the two register to be different? Or can they both be $f2?

Answer 1

Instructions operate on the type of registers laid out in its specifications, if you want to know read it.

Format: ADDI rt, rs, immediate MIPS32
Purpose:
To add a constant to a 32-bit integer. If overflow occurs, then trap.
Description: rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and
an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rt.
Restrictions:
None
Operation:
temp ← (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate)
if temp32 ¹ temp31 then
SignalException(IntegerOverflow)
else
GPR[rt] ← temp
endif
Exceptions:
Integer Overflow
Programming Notes:
ADDIU performs the same arithmetic operation but does not trap on overflow.

So no addi cannot operate on coprocessor registers

Format: CVT.S.D fd, fs MIPS32
CVT.S.W fd, fs MIPS32
CVT.S.L fd, fs MIPS64
MIPS32 Release 2
Purpose:
To convert an FP or fixed point value to single FP
Description: fd ← convert_and_round(fs)
The value in FPR fs, in format fmt, is converted to a value in single floating point format and rounded according to the
current rounding mode in FCSR. The result is placed in FPR fd.
Restrictions:
The fields fs and fd must specify valid FPRs—fs for type fmt and fd for single floating point. If they are not valid, the
result is UNPREDICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE.
For CVT.S.L, the result of this instruction is UNPREDICTABLE if the processor is executing in 16 FP registers
mode.
Operation:
StoreFPR(fd, S, ConvertFmt(ValueFPR(fs, fmt), fmt, S))
Exceptions:
Coprocessor Unusable, Reserved Instruction
Floating Point Exceptions:
Invalid Operation, Unimplemented Operation, Inexact, Overflow, Underflow

It doesn’t say that fd and fs have to be different so unless is some other rule about source and destination register can’t be the same you can use one.