Question

For example:

When the MEM CTRLER wants a instruction register to be populated with the DATA which the next ADDR REGISTER points to.

Does it send a signal to the ADDR REGISTER to place the next ADDR on the ADDR bus or does the ADDR go to the MEM CTRLER and is placed on the BUS by the MEM CTRLER?

Answer 1

First off, the memory controller does not want to do anything (except refresh DRAM, but thats overcomplicating things for this example).

In many basic CPUs, the rough sequence of events is:

1. CPU encounters a LOAD instruction (either direct instruction or through microcode). The address register is then loaded with the payload from this instruction (the address to read). The address register in this simple example is directly coupled to the ADDRESS bus. Note that loading INSTRUCTIONS is the same sequence, but may occur on a separate bus (Harvard architecture)
2. The CPU assets the READ line.
3. The memory controller does whatever it needs to do in order to perform a read.
4. The memory controller places the data on the DATA bus.
5. The memory controller may or may not assert a DR (Data Ready) signal.
6. Either by waiting a specific number of cycles, or waiting for the DR signal, the CPU then latches the contents of the DATA bus.
7. The DATA bus latch is loaded into the target register.

This is a gross simplification of a modern CPU. Introducing cache, pipelines, out of order execution, makes this a much more involved sequence.