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Asked: 2026-06-15T12:28:11+00:00

For Intel I use: mov, eax, 2h cpuid it gives descriptor decode value –

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For Intel I use:

mov, eax, 2h
cpuid

it gives “descriptor decode value” – ok;

For AMD I use:

mov, eax, 80000005h
cpuid

It gives associativity and entries for 4MB in eax (4KB in ebx).

Here it is :

EAX = FF30FF10 EBX = FF30FF20″
FF – full assoc. data, 48d entries data, FF – full assoc. instr, 16d entries instr

So I have both 4KB and 4MB or what?

P.S. i`m right that TLB page and L1 cache – different things? Or maybe L1 instr. cache size is what I need?

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  1. Editorial Team

    This entry on wikipedia may help you clear up some of the confusion on the different TLB sizes. It’s under the heading “Multiple TLB’s”:

    For instance, Intel’s Nehalem microarchitecture has a four-way set associative L1 DTLB with 64 entries for 4 KiB pages and 32 entries for 2/4 MiB pages, an L1 ITLB with 128 entries for 4 KiB pages using four-way associativity and 14 fully associative entries for 2/4 MiB pages (both parts of the ITLB divided statically between two threads)1 and a unified 512-entry L2 TLB for 4 KiB pages,[2] both 4-way associative.[3]

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