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For school I’m working on writing an ARM simulator. In the ARM ARM (http://www.eecs.umich.edu/~prabal/teaching/eecs373-f11/readings/ARMv7-M_ARM.pdf) the calculate the second and third highest bit for the branch offset as I1 = NOT(J1 EOR S); and I2 = NOT(J2 EOR S); (ARM ARM pg 239). Does anyone know why it’s this way? For some reason it seems to be causing me errors.
It’s a bit of a puzzler but it appears to be a technique to map the I1 and I2 bits into valid instruction encodings.
Thumb branch instructions are encoded as a pair of 16-bit sub-instructions. Each 16-bit sub-instruction needs its own distinct instruction encoding.
The ‘S’ bit is a sign bit so we can see there’s no way to distinguish Encoding T3 and Encoding T4 from the first 16-bit sub-instruction.
In the second sub-instruction bit 12 distinguishes Encoding T3 and T4. However, using I1 and I2 directly would clash with existing instructions so they’re munged into one of four encodings, each determining the range of the branch.