Forgive a newbie, I don’t even know how to ask this question properly:
I have a file which is currently loaded into a memory bank, and I’d like to split it across four different memory banks.
I have some system verilog code which uses a line very like this:
$readmemh(mem_file, memories.ram);
to read in a hex file (say it’s 65536 bytes long) to some memory.
Now I want to split the memory into four parts, and put the first quarter (16384 bytes) into a block, the second quarter into another, etc…
One obvious way to do this is to split the hex file using head, tail, etc, as part of the build process that makes it, and then pass in all the new filenames at simulation time, and have statements like
$readmemh(mem_file_1stbit, memories.ram1);
$readmemh(mem_file_2ndbit, memories.ram2);
$readmemh(mem_file_3rdbit, memories.ram3);
$readmemh(mem_file_4thbit, memories.ram4);
But that seems to couple the firmware build process, simulation script, and verilog design far too much for my taste.
A greatly superior solution (in my opinion), would be to modify the verilog code to say something like:
$readmemh(mem_file, memories.ram1, 0, (1<<14)-1);
$readmemh(mem_file, memories.ram2, (1<<14), (2<<14)-1);
$readmemh(mem_file, memories.ram3, (2<<14), (3<<14)-1);
$readmemh(mem_file, memories.ram4, (3<<14), (4<<14)-1);
But it doesn’t look like verilog will let me do this sort of thing.
Can anyone come up with a neat construction that will achieve the same result?
This little snippet seems to do the business. It does introduce an intermediate load of stuff that I rather hope won’t end up getting synthesised.
I’ll go with this sort of thing. If anyone who actually knows what they’re doing wants to tell me why this is a bad idea, I’d be most grateful.