Question

Good Day and thanks for looking at this question

I am using VCSMX (a June 2011 version) for simulating a core with a record type interface. The core is written all in VHDL. I am using an Systemverilog (SV) Testbench to excite this core.

The record looks something like:

type ll_port is record
    frame_name      : std_logic_vector(WIDTH-1 downto 0);
    frame_valid     : std_logic;
 .
 .
 .
end record;

I read that VHDL record type is the same as struct in SV. However, this seems to still be an unsupported feature in VCSMX when I try to implement a ll_port struct in SV. The sure shot solution is to decompose the record port into std_logic and std_logic_vector.

However, this record type in VHDL will be used several times and several cores will be interacting in the final system, making the decomposition of every record port really cumbersome.

I was looking to see how to handle this problem and what advice I can get in this matter. I already have a custom simulation infrastructure in SystemVerilog and would like to know if there are workarounds to this issue.

RRS

Answer 1

Not the answer you’re looking for, but I think you’re stuck with decomposing the port.

To be honest, records as port types in VHDL make me nervous as they’ve been a great way of breaking all sorts of tools over the years. I know of synthesis tools that used to reverse connections (MSB <-> LSB) if records were used on ports and so many companies had house rules banning the use of records in this way.

You could write some functions on either side to flatten the record into a single wide std_logic_vector and then reconstruct it, but I think that’s more work and less readable than just having ports for each field.