Question

Homework for designing risc processor. I have 16 bit PC like this

signal pc_din, PC, pc_rel, pc_dir, pc_inc : std_logic_vector(15 downto 0); -- pc datapath
pc_inc <= pc + 1;
pc_dir <= pc(15 downto 13) &  ADD;
pc_rel <=  pc_inc + ext(15 downto 0);

Mux for PC source is

with PCSrc select
pc_din <= A when from_A,
pc_rel when from_pcrel,
pc_dir when from_pcdir,
pc_inc when from_pcinc,
(others=>'-') when others;

I have LPM generated 16 by 256 single port ROM for instruction memory

component mem
PORT(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock   : IN STD_LOGIC ;
q   : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;

PC register port map is

pc_reg: reg Port map (clk=>clk, rst=>rst, D=>pc_din, Q=>PC, we=>ldPC);

Now the question is how can i port map the mem component because pc is 16 bit and address is 8 bit

rom: mem port map(address=>???, clock=>clk, q=>instr_din);

Answer 1

It is normal for the available memory to be smaller than the memory space the CPU can access.

That just means you need to design a memory map for your processor, and implement it. Are there any known constraints to help?

For example, some processors set the PC to 16#FFFE# on reset, others to 0. This means you need a page of program memory either at the top of the memory space, or at the bottom.

Also you need to consider whether that PC is a byte address or a word address; and (if it is a byte address) whether it will ever be odd ( in which case you need to support unaligned addresses). Since you say it is a RISC CPU I am going to assume you don’t need to support unaligned addresses, but this should be specified somewhere.

If it is byte addressed, you need to translate the byte address to the correct word address for your ROM – supporting aligned accesses only, this is easy; just drop the LSB.

When you have designed your memory map, you can design a decoder that only selects the program ROM when the high order address bits are the correct value. It is sometimes possible to simplify this decoding by mapping the ROM at multiple addresses (treating some address bits as don’t cares) but this is not always a good idea as it can lead to problems expanding the memory later.

So, assuming byte addressing, aligned access only, and you know what your memory map looks like:

ROM_Address <= PC(8 downto 1);
ROM_Enable  <= some expression involving PC(15 downto 9);

and you are done.