How are interrupts handled on SMP (Symmeteric multiprocessor/multicore) machines? Is there only one memory management unit or more?
Say two threads, A and B running on different cores touch a memory page (at the same time) which is not there in the page table, in which case there will be a page fault and a new page is brought in from the memory.
What is the sequence of events which will happen? If there is one memory management unit, to which core is the page fault forwarded to? How does the kernel handle it? Are there multiple instances of the kernel, each one running on a different core? If so, how do they synchronize on such events as page fault handling?
On multicore/multiprocessor architectures, an APIC is used to route interrupts to cores/processors. As the name implies, APICs can be programmed to do the routing as desired.
Regarding the synchronization of the kernel: This depends on the kernel/OS. You can either use a scheme with locking (although IPIs might be necessary on non-cachecoherent architectures) or you can also use your suggested approach of running a kernel on every core and use some kind of explicit inter-kernel communication.
Barrelfish is an example of an OS running multiple kernels. If you are interested in that kind of architecture, you might want to read the paper “The Multikernel: A new OS architecture
for scalable multicore systems“