Question

How would one create a make file for running e.g. xml parser with the following command line command

gcc source.c -I/usr/include/libxml2 -lxml2 -o output

I use this to include libxml when compiling using the command line.

How would this be made using a make file instead of the command line usage?

Answer 1

SOURCES:=source.c
OBJECTS:=$(SOURCES:%.c=%.o)
CC=gcc
CFLAGS=-g -Wall -I/usr/include/libxml2
LD=gcc
LDFLAGS=
LIBS=-lxml2
TARGET:=output



all: $(TARGET)

$(TARGET): $(OBJECTS)
        $(LD) -o $@ $(OBJECTS) $(LDFLAGS) $(LIBS)

.c.o:
        $(CC) $(CFLAGS) -c $< -o $@

depend:
        $(CC) $(CFLAGS) -MM $(SOURCES) > .depend

clean:
        rm -f $(OBJECTS) $(TARGET) 

.depend: depend

include .depend

You can use this as a template, then add to/modify SOURCES, TARGET, CFLAGS, LDFLAGS and LIBS. Makefiles require TABs for indentation – so you’ll need to fix the spaces if you copy-paste this.