Question

http://www.cprogramming.com/tutorial/makefiles_continued.html explains implicit targets:

There are some actions that are nearly ubiquitous: for instance, you might have a collection of .c files that you may wish to execute the same command for. Ideally, the name of the file would be the target; using the implicit target “.c” you can specify a command to execute for any target that corresponds to the name of a .c file (minus the .c extension).

However, when I try it, the implicit target is simply ignored. My test makefile is as follows:

Default: Foo.bar
    echo "In default."

.bar:
    echo "In .bar."

make: *** No rule to make target `Foo.bar', needed by `Default'.  Stop.

What am I missing?

Answer 1

Try:

default: foo.bar
    echo "In default."

%.bar:
    echo "In .bar."

You may be asking about old-style suffix rules – for example this rule:

.c.o:
    cc -c $<

tells make how to build a .o file from a .c source. The form with the ‘%’ is known as a pattern rules and is more “modern”. I suggest you read the GNU Make manual, which is very informative about such stuff, and easy to read.