Question

I am coding a basic combinational circuit in VHDL, which has an AND gate with two inputs a and b. The output of this “t” is OR’ed with a negated input “c”. This output “s” is then NAND with “a” to give the final output “d”.

Here’s the code.

library ieee;
use ieee.std_logic_1164.all;
entity logicgate is
port(a,b,c: in std_logic;
d: out std_logic);
end logicgate;

architecture arch_logicgate of logicgate is
begin
signal s: std_logic;
signal t: std_logic;
t<= a and b;
s<= (not c) or t;
d<= a nand s;
end arch_logicgate;

Transcript:

-- Compiling architecture arch_logicgate of logicgate
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): (vcom-1136) Unknown identifier "s".
# 
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): Type error resolving infix expression "nand" as type ieee.std_logic_1164.STD_LOGIC.
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(15): VHDL Compiler exiting

I know I am missing out on the basics. Please help me out.

Answer 1

The first error message:

** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error

arises because there are declarations in the execution region.

Put them in the declaration region, before begin

architecture arch_logicgate of logicgate is
   signal s: std_logic;
begin
   ...