Question

I am designing a basic AES algorithm on verilog, and I need to split a 128 bits array into 16 parts each one of 8 bits.

For example (basic 8 bit example), if I receive 10111011 I need to generate 4 outputs 10 11 10 11

Answer 1

A double packed array works:

reg [127:0] in;
wire [15:0] [7:0] out_1 = in; // msb in entry 15
wire [0:15] [7:0] out_2 = in; // msb in entry 0

If only one byte is needed to be read at a time, it can be done Verilog-2001 or SystemVerilog as:

reg [127:0] in;
reg [3:0] idx;
wire [7:0] out = in[8*idx +: 8];