Question

I am doing a D flip flop with VHDL
This is the code:

LIBRARY STD,WORK;
USE STD.standard.all;
entity FlipFlopD is 
port(
  input, clock :in bit;
  output :out bit
);
end FlipFlopD;

--Architecture of the entity
Architecture FlipFlopDfunc of FlipFlopD is 
begin 
  PROCESS (clock)
  BEGIN
    IF (clock’EVENT AND clock=‘1’) THEN 
      output <= input; 
    END IF;
  END PROCESS;
end FlipFlopDfunc;

These are errors I get when I try to synthesize it:

Line 16. Unexpected symbol read: ?.
Line 16. Unexpected symbol read: ?.
Line 16. parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR

The error in line 16 is extrange to me because I don´t see any ‘?’ symbol in this line:

IF (clock’EVENT AND clock=‘1’) THEN 

Does anyone know how to correct it?
Does anyone know what to do with this error parse error, unexpected IDENTIFIER, expecting COMMA or CLOSEPAR?

By the way, I am doing my design using ISE 9.2
Thank you for your help.

Answer 1

Are you sure you use the correct type of single quote (') signs? If they are like this in your VHDL code I guess they are wrong.

IF (clock'EVENT AND clock='1') THEN