Question

I am getting the following error with my code: ** Failure: (vsim-3808) Incompatible modes for port "d_out".

I specified a new component, defined its entity, connected its ports, everything seemd ok and even compiled but when I ran a tb it wrote an error that appears in the headline

this is part of the code:

signal jal_nor_out: std_logic;
 jal_unit: jal_nor
port map(
data_in(5 downto 0) => instruction(31 downto 26),
d_out => jal_nor_out
);
jal_writedata_mux : Mux_2to1_xN
port map(
    sel => jal_nor_out,
    d_in1 => WriteData,
    d_in2 => pc_inc,
    d_out => data_mux_out
    );

and on another file I have:

    entity jal_nor is
    port(
    data_in : in std_logic_vector(5 downto 0);
    d_out : out std_logic
    );
end jal_nor;
architecture bhv of jal_nor is
    begin
        process (data_in) 
          begin
            if data_in="000011" then
                d_out <= '1';
            else
                d_out <= '0';
            end if;
        end process;
    end bhv;

this is the Mux code

    entity Mux_2to1_xN is
  generic(
           WIDTH :     integer := 32);
  port(
        sel   : in  std_logic;
        d_in1 : in  std_logic_vector((WIDTH - 1) downto 0);
        d_in2 : in  std_logic_vector((WIDTH - 1) downto 0);
        d_out : out std_logic_vector((WIDTH - 1) downto 0));
end Mux_2to1_xN;

any help?

Answer 1

Sounds like the compiler thinks you have told it two different things about the ports. Have you used any component declarations?

debugging advice:

Make a smaller testcase – keep chopping code out until you have the tiniest subset of the code which causes the error. Take out ports which don’t matter, signals that are unused, everything else. In the process of doing this you’ll find a very small code subset is causing the problem, and probably be able to fix it yourself. If not, you have a small self-contained piece of code you can post here for us to look at. Just the tiniest code, not with lots of lines commented out. And make sure what you post compiles to the same error…