Question

I am implementing a simple adder. However, I have a need for a bit of a unique twist.

What I’m implementing is a “roll over” feature across a Code Segment(CS) register and an Instruction Pointer(IP) register. So, when you do a relative jump by +20, and IP is 254, IP will end up rolling over to 18, and CS will end up incrementing by 1.

This part is easy, the hard part is the opposite direction. Detecting a borrow for when, say the jump is -20 and IP is at 0, it needs to decrement CS by 1 and make IP roll-under to 236.

So far my code is

entity carryover is 
  port(
    DataIn: in std_logic_vector(7 downto 0);
    SegmentIn: in std_logic_vector(7 downto 0);
    Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
    DataOut: out std_logic_vector(7 downto 0);
    SegmentOut: out std_logic_vector(7 downto 0);
   );
end carryover;

architecture Behavioral of carryover is
  signal temp: std_logic_vector(8 downto 0);
begin
  --treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
  temp <= std_logic_vector(unsigned("0" & DataIn) + (unsigned)Addend);
  DataOut <= temp(7 downto 0);
  SegmentOut <= unsigned(SegmentIn) + 1 when (not temp(8)) and (not Addend(7) 

end Behavioral;

But I can’t figure out how to detect borrows. Is there a clean way to do this?

Update

My new code is this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.tinycpu.all;

entity carryover is 
  port(
    EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
    DataIn: in std_logic_vector(7 downto 0);
    SegmentIn: in std_logic_vector(7 downto 0);
    Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
    DataOut: out std_logic_vector(7 downto 0);
    SegmentOut: out std_logic_vector(7 downto 0)
--    Debug: out std_logic_vector(8 downto 0)
   );
end carryover;

architecture Behavioral of carryover is
  signal temp: std_logic_vector(8 downto 0);
begin
  --treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
  process(DataIn, SegmentIn,Addend, EnableCarry)
  begin
    temp <= std_logic_vector(signed('0' & DataIn) + signed(Addend(7) & Addend)); 
    if (EnableCarry and ((not Addend(7)) and (DataIn(7)) and temp(8)))='1' then 
      SegmentOut <= std_logic_vector(unsigned(SegmentIn)+1);
    elsif (EnableCarry and (Addend(7) and (not DataIn(7)) and temp(8)))='1' then 
      SegmentOut <= std_logic_vector(unsigned(SegmentIn)-1);
    else
      SegmentOut <= SegmentIn;
    end if;
  end process;
  --Debug <= Temp;
  DataOut <= temp(7 downto 0);
end Behavioral;

Addition of signed numbers works as planned, and Temp is always the correct result now, yet SegmentOut is always equal to SegmentIn. I don’t understand why because for SegmentIn + 1, I actually hand-computed the inputs for Addend=0x04, DataIn=0xFE, SegmentIn=0x00, and CarryEnable=1 and the if statement equals out to (1 and ((not 0) and 1 and 1))='1' and yet, SegmentOut never changes. Does anyone see a problem with how this is implemented?

Answer 1

Overflow occurs when summands sign bits are equal but not equal to sum sing bit:

A = + 12, B = + 4.            A = + 4, B = – 12
А = 0.1100                    A = 0.0100
В = 0.0100                    B = 1.0100
    ------                        ------   
C   1.0000                    C   1.1000
As = Bs, Cs = 1 – overflow    As != Bs - not overflow.

As DateIn is always positive, overflow can occur only with carry (for both positive numbers). So you should change your statement to (and probably unite these two somehow):

SegmentOut <= unsigned(SegmentIn) + 1 when (not Addend(7) and temp(7)); 
SegmentOut <= unsigned(SegmentIn) - 1 when (Addend(7) and temp(7));

Here is a Truth table:

Addend(7) DataIn(7) temp(7)| Carry Borrow
0         0         0      | 0     0
0         0         1      | 1     0
1         0         0      | 0     0
1         0         1      | 0     1

EDIT: as Paul Seeb said:

SegmentOut <= unsigned(signed(SegmentIn) + signed(Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & "1")) when (temp(7) and CarryFlag);