I am new to linux development.
I wrote a project using MPI and cuda. When
it gets bigger and bigger, I realize that I
need a Makefile now. So I learned how to write
one. The Makefile works, but will only compile
cpp files even if I have both of the following
lines in my Makefile:
.cpp.o:
$(CC) $(CCFLAGS) $<
.cu.o:
$(NVCC) $(CCFLAGS) $<
Any idea why this is happening? Thanks.
UNDERSTANDING MAKE
Make is all about generating missing files.
If you have TWO rules that generate the SAME file upon existence of a source then the first one in make’s list that actually has a source file present will get invoked. So for instance if you have the rules:
and you have two files, foo.c and bar.cpp then you can type:
it will use the first rule… and when you type
it will use the second rule.
Now suppose you have TWO files
foo.candfoo.cppHere make has to make a choice as to which takes precedence. Make uses suffixes of files intimately for its build rules. What is considered a suffix is controlled by the
.SUFFIXESdirective.The
.SUFFIXESdirective has a default built-in value that defines common suffixes such as .c .cpp .cc .o etc. in a particular order. If we want to change the order of precedence we clear that out with a blank line in Makefile i.e.:and then follow it with our definition:
if you don’t blank the line out, then make just appends the listed suffixes to its current list, that way multiple makefiles can simply add new suffixes without worrying about breaking each other.
Now since the .cpp is before .c the
.cpp.orule will take precedence (in case foo.cpp and foo.c are both present)NOTE: Yes there is a “.” before the words SUFFIXES and yes it is all capital letters.
Try to play with this Makefile to see the effects:
Make is very very powerful, and quite well documented so well worth the read. GNU make, which is probably the strongest implementation with amazing extensions has made me a lot of money in the past 🙂 enjoy the experience.