Question

I am new to VHDL, working on a homework assignment.

I have a very simple clock divider using a generic. (It’s a counter/divider.)

-- the actual divider will be 2.1e6 or so (25Mhz down to 15hz)
run_divider : clk_divider
--pragma synthesis off
    generic map(clkmax => 4) -- simulation
--pragma synthesis on
    generic map(clkmax => 50000) -- synthesis
      port map( clk_in => mclk,
                reset => rst,
                clk_out => divider_out );

I partially used Equivalent of #ifdef in VHDL for simulation/synthesis separation? with the pragma above. However, this only works in synthesis but is a syntax error in simulation.

Other than using an external tool (M4, C preprocessor as another answer suggested), is there a better way to have separate code for synthesis vs simulation? I’d like to stopy worrying about these constants when I switch between synthesis to simulation.

Answers to How to convert 24MHz and 12MHz clock to 8MHz clock using VHDL? tell me the counter/divider is not an optimal solution but it’s simple enough for my homework 🙂

My full divider code is here:
https://github.com/linuxlizard/vhdl/blob/master/divider.vhdl

Thank you!

Answer 1

As simon says, you can use a flag with a generate – if you put this code into some utility package, you can use it throughout your design. Or just add it to the local architecture if it’s a one-off:

constant in_simulation : boolean := false
--synthesis translate_off
                                    or true
--synthesis translate_on
;

A potentially useful alternative is:

constant in_simulation : integer  := 0
--synthesis translate_off
                                    + 1
--synthesis translate_on
;

constant in_synthesis : integer  := 1
--synthesis translate_off
                                    - 1
--synthesis translate_on
;

Which can be used, in your case, to do:

constant clkmax_coefficient : integer := 4*in_simulation + 50000*in_synthesis;

run_divider : clk_divider
    generic map(clkmax => clkmax_coefficient)
...