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Asked: 2026-05-26T11:37:15+00:00

I am programming the 8051 instruction set in VHDL in Xilinx. After writing the

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I am programming the 8051 instruction set in VHDL in Xilinx. After writing the logic and generating the synthesis report, I saw that the Delay is 13.330ns (frequency of 75.020 MHz) with Levels of Logic = 10.

This value is pretty less (the frequency) and I need to beef it up but I am not able to understand what/where is the delay using the synthesis report.

This is the part of the report which talks about the timing:

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_div1'
  Clock period: 13.330ns (frequency: 75.020MHz)
  Total number of paths / destination ports: 156134 / 3086
-------------------------------------------------------------------------
Delay:               13.330ns (Levels of Logic = 10)
  Source:            SEQ/alu_op_code_1 (FF)
  Destination:       SEQ/alu_src_2L_7 (FF)
  Source Clock:      clk_div1 rising
  Destination Clock: clk_div1 rising

  Data Path: SEQ/alu_op_code_1 to SEQ/alu_src_2L_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             40   0.591   1.345  SEQ/alu_op_code_1 (SEQ/alu_op_code_1)
     LUT4:I1->O            2   0.643   0.527  ALU1/ci32_SW0 (N2251)
     LUT4:I1->O            1   0.643   0.000  ALU1/adder_comp/C11_F (N1292)
     MUXF5:I0->O           3   0.276   0.531  ALU1/adder_comp/C11 (ALU1/adder_comp/C1)
     MUXF5:S->O           12   0.756   0.964  ALU1/adder_comp/C21 (ALU1/adder_comp/C2)
     LUT4:I3->O            8   0.648   0.760  ALU1/ans_L<5>104 (ALU1/ans_L<5>104)
     LUT4:I3->O           17   0.648   1.054  ALU1/ans_L<7>95_SW0 (N264)
     LUT4:I3->O            1   0.648   0.000  SEQ/alu_src_2H_and000055_SW3_F (N1304)
     MUXF5:I0->O           1   0.276   0.423  SEQ/alu_src_2H_and000055_SW3 (N599)
     LUT4_D:I3->O         15   0.648   1.049  SEQ/alu_src_2L_mux0005<7>121228 (N285)
     LUT4:I2->O            1   0.648   0.000  SEQ/alu_src_2H_mux0007<6> (SEQ/alu_src_2H_mux0007<6>)
     FDE:D                     0.252          SEQ/alu_src_2H_1
    ----------------------------------------
    Total                     13.330ns (6.677ns logic, 6.653ns route)
                                       (50.1% logic, 49.9% route)

Can someone explain what is happening?

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1 Answer

  1. Editorial Team

    Look at the names in the report and compare to your source code.

    Basically, you have just combinational logic flowing in the “SEQ” instance from the ALU op code to an ALU output signal “alu_src_2L”:

    Source: SEQ/alu_op_code_1 (FF)
    Destination: SEQ/alu_src_2L_7 (FF)

    Looking at the details, you can see that in this particular path, most of the time is used in your ALU “ALU1”, and specifically in the adder/comparison logic “adder_comp”. If you want to have less delay in this path, you are going to have to either optimize the logic or cut the path with another register (and make the rest of the design still work with that change).

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