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Editorial Team
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Editorial Team
Asked: June 11, 20262026-06-11T18:28:25+00:00 2026-06-11T18:28:25+00:00

I am seeking help, most importantly from VMEbus experts. I am working on a

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I am seeking help, most importantly from VMEbus experts.

I am working on a project that aims to setup a communication channel from a real-time powerpc controller (Emerson MVME4100), running vxWorks 6.8, to a Linux Intel computer (Xembedded XVME6300), running Debian 6 with kernel 2.6.32.
This channel runs over VME bus; both computers are in a VME enclosure and both use the Tundra Tsi148 chipset. The Intel computer is explicitly configured as the system controller, the real-time computer is explicitly not.

Setup:
For the Intel computer I wrote a custom driver that creates a 4MB kernel buffer, and shares it over the VME bus by means of a slave window;
For the real-time computer I setup a DMA transfer to repeatedly forward blocks of exactly 48640 bytes; filled with bytes of test data (zeros, ones, twos, etc), in quick succession (once every 32 milliseconds, if possible)
For the Intel computer I read the kernel buffer from the driver, to see whether the data arrives correctly, with a hand-started Python program.

Expectation:
I am expecting to see the same data (zeros, ones etc) from the Python program.
I am expecting transmission times roughly corresponding to the chosen bus speed (typically 290 us or 145 us, depending on bus speed), plus a reasonable DMA setup overhead (up to 10us? I am willing to accept larger numbers, say hundreds of usecs, if that is what the bus normally needs)

Result:

  • Sometimes data does not arrive at all, and “transmission” time is ~2000 us
  • Sometimes data arrives reliably, but transmission time is ~98270us, or 98470us, depending on the chosen bus speed.

Questions:
How could I make the transmission reliable and bring down these aweful latencies?
What general direction should I search next?

(I would like to tag with VMEbus if I could)

Many thanks

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  1. Editorial Team
    Editorial Team
    2026-06-11T18:28:26+00:00Added an answer on June 11, 2026 at 6:28 pm

    My comments on the question describe how I got the bus working:
    – ensure 2eSST320 on both sides of the bus
    – ensure that the DMA transaction used a valid block size (the largest valid was 4096 bytes)

    I achieved an effective speed of 150MBytes/s (the bus can achieve 320MBytes/s but the tsi148 chip is known for causing significant overhead). This is good enough for me.

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