Question

I am trying to build a model to compare the input for a particular bit pattern.

For example, if I have to check for input pattern 1110, I build a model with 3 delay elements get the input and Concatenate it and then use a comparator to compare with 14(Hex E).

Currently, I need to do a pattern matching for 128 bits. Going by previous instance, I can ideally build the similar model of using 127 Delay elements and compare Blocks.

But I would like to know if there is a optimal and “better” way to do it.

Looking forward to some suggestion in this regard.

If you are interested, here is the small model I built to extract 8 bits:

Answer 1

What you have described is a fine generic approach – it assumes nothing about the patterns you want to detect.

You might be able to do something different if the pattern is (for example) a long string of 1s then 0s (create counters to count those lengths and flag a match if the counters reach the right values)

I think you could make your diagram a little easier (maybe) if you created a block with the z^-1 and concat inside. Then when you pass in the input, you can delay it and concat it with the previous stage’s output (also passed in).

As another aside, this is trivially described in VHDL as a shift register (one line of code) and a matcher (another line of code).

You could build a similar thing in an m-code block (in a similar couple of lines), using persistent variables for registers, but if you want to instantiate more than one instance of the block you’re out-of-luck as the persistent storage is shared across them!