Question

I am trying to define a function in VHDL but I get

Error: tst.vhd(4): near “subtype”: syntax error

Here is the code

subtype word10 is bit_vector(9 downto 0);
subtype word8 is bit_vector(7 downto 0);

function tst (input : in word10) return word10 is
    variable tmp : word10;
    -- code here
    begin

    return tmp;
end tst;

entity tester is
end;

architecture tst of tester is
begin
end;

It is the first time I am coding in VHDL and I cant figure out what is the error.

Any ideas?

Answer 1

The problem is the things you are attempting to define (subtypes and functions) need to be declared inside of a library unit (package or entity) or some other body, not just hanging out on their own. Try moving the declarations to the tester entity (ie: after the “entity tester is” line):

entity tester is
    subtype word10 is bit_vector(9 downto 0);
    subtype word8 is bit_vector(7 downto 0);

    function tst (input : in word10) return word10 is
        variable tmp : word10;
        -- code here
        begin

        return tmp;
    end tst;
end tester;

Exactly where you declare your subtypes and functions will depend on the scope where you need them to be visible. If you need them accessible across your entire design, they are typically gathered together and declared in a package.