Question

I am trying to ‘fire’ off the compilation by making all dependencies in a list of items, which are themselves targets.

From the answer (last, posted by Carl..) given in seems to suggest that something like this is possible.

Wildcard targets in a Makefile

---

all:    $(OBJECTS)

OBJECTS = foo.o bar.o

bar.o:  bar.c
        @echo make $@

foo.o:  foo.c
        @echo make $@

.PHONY: all

My question is, when I run make I get the following, I cannot seem to get it to compile.

make: Nothing to be done for `all'.

Answer 1

Reverse the order of the first two lines, like so:

OBJECTS = foo.o bar.o

all:    $(OBJECTS)

In your example, when Make gets to the all rule, OBJECTS has not yet been defined, so it resolves to this:

all:

Make sees a rule with no commands and no prerequisites– nothing to be done.