Question

I am trying to implement a 7-segment counter using VHDL.

The counter starts from 0 and increments an integer value to a max of 9999.

The value is passed to a bloc that is supposed to “split” the number into digits so that i can display them on the 7-segment which are multiplexed…

I have already done this on a PIC using many methods such as Interrupts… but now that i am trying to do this on a FPGA (Xilinx Spartan 3E Starter Board to be exact) i noticed while implementing the code i’ve wrote that i can’t use neither division nor modulus because they cannot be implemented…

Edit: I know i could just map the values 0..9999 each alone but that is far far fetched.

Surely there is another way, but i can’t think of it.

Any hint on a workaround would be very appreciated!

Answer 1

Well, if your number is in decimal, just extract the bits containing each digit and send them to your display multiplexor. The LSD is num[3:0], the MSD is num[15:12], etc.