Question

I am trying to model a T Flip Flop using VHDL.

library ieee;
use ieee.std_logic_1164.all;
entity tff is
    port (
        clk: std_logic;
        t: in bit;
        q: out bit;
        qbar: out bit);
end tff;

architecture tff_arch of tff is
begin
    process(clk)
    begin
        if (clk = '1' and t = '1')
        then
            q <= not q;
            qbar <= not qbar;
        end if;
    end process;
end tff_arch;

But the error i am getting is

Error: CSVHDL0168: tff.vhdl: (line 17): Identifier 'q' is not readable
Error: CSVHDL0168: tff.vhdl: (line 18): Identifier 'qbar' is not readable

The reason of error i think is, i am using “not q”, when q has not been initialized. Correct me here, if i am wrong.

And what to do to get around this problem? I have modeled D Flip flop and its test bench waveform correctly using Symphony EDA free version.

Answer 1

q is an output of the entity.

You can’t read an output. It’s that simple.

You need an internal version that you use for the feedback loop, and then q <= local_q;