Question

I am trying to port some SystemVerilog code to C++/SystemC, and am a bit stuck on a couple lines where I see strange array indexing. Here is a simplified version of what I see.

typedef enum bit [2:0] {enu_red, enu_blue, enu_green} typ_enum; 

typedef struct packed {
    bit [3:0] field1;
    bit [3:0] field2;
} typ_struct;

...

var int arr_ints[typ_struct];
var int que_ints[$];

typ_struct obj_struct;
typ_enum   obj_enum;

int i = 3;

// assume all the declared variables hold valid values at this point
// also assume que_ints[i] is valid

if ((!arr_ints[obj_struct][1]) // these two lines are the problem
    && (que_ints[i][obj_struct])
)
begin
    // do something
end

Now after I port this code I get some compiler errors which I completely understand, because the original code doesn’t look exactly right to me. In the first line of the if statement, it looks like trying to index an integer type with a boolean value. In the second it looks like trying to index an integer type with an enumerated value. Yet this code apparently works. Can someone please explain what it is doing?

Answer 1

This does bit slicing of the integer type. You will access the actual bits of the underlying int representation.

If que_ints[5] is integer 0xdeadbeef, then:

• que_ints[5][3] is 1
• que_ints[5][7:4] is 0xe.

In SystemC the range() function is the corollary.