Question

I am trying to study for a test where I have to know something about MIPS and assembly code. I will try to write what I think is a correct answer for the given questions but I’m not sure if I’m right

1. Can direct operand 32 bit operand in MIPS contain any 32 bit value?

   I think “no – never” because first 16 bits are reserved for opcode and source + final registers. Is it right or are there some instructions that can contain any 32-bit value?

2. We have times for instruction (IF = 400ps, ID = 500ps, EX = 450ps, MEM = 500ps, WB = 150ps)

   Whats the clock tact for

   a) processor without pipeline?
   b) processor with pipeline?

   I think that a) is 2000ps (sum of all times) and b) 500ps (the biggest time in a table) but again, Im not sure.

3. I have the following assembly code:

   0x0000      addi t0, $0, 5
   0x0004  loop:   beq t0, $0, done
   0x0008      nop
   0x000C      lw t1, 0x4($0)
   0x0010      lw t2, 0x24($0)
   0x0014      addi t0, t0, -1
   0x0018      j loop
   0x001C      nop
   0x0020  done
   

   I am not 100% sure what it does (because I don’t fully understand what is the result of 0x4($0) operation in load). I know that there is a for cycle (for t=5, ,t >0 t--).

   The question is – what is hit rate and miss rate of this cache and how do you calculate it?

If you could answer at least the first two questions, it would be great.

Answer 1

1. If you are talking about MIPS 32 bits, then of course, it is not possible for type I instructions to contain a 32 bits immediate. The layout for such a instructions is (opcode, rs, rt, IMM), being their sizes (6, 5, 5, 16) bits. So the immediate value is just 16 bits size. Of course if the architecture is 64 bits, then you could have longer immediate values.

2. I assume you refer to the latency of instruction execution. As you well point out, if there is no pipeline you need to add the time for all the stages. If the processor uses a pipeline, the clock must be set to match the slowest stage. In your case that is 500ps, both for decoding and memory stages.

3. lw t1, 0x4($0) loads a word from memory address 0x4 ($0 refers to register 0 which always contains zero) and stores the value into t1. So if you look carefully at the code, you will see that it always loads data from positions 0x4 and 0x24. Assuming the cache is empty at the beginning, then you will have two misses in the first iteration and no other miss during the following ones. Therefore the miss rate will be (1*2) / (5*2) = 2/10 = 1/5. You must take into account, however, whether the cache transfers data in blocks. In that case the first load may transfer a big block containing for instance 64 bytes. That will make that the second load operation would not miss, so the miss rate would be reduced to 1/10. But I do not think this is the case with this simple processor.

FYI, here you have lots of information about MIPS architecture and ISA. You may also be interested in a classic book on computer architecture: Computer Architecture: A Quantitative Approach