Question

I am trying to understand the diagram for register write operation in MIPS(Single Cycle Data Path). I do not get why do we need to AND the output of the decoder to the write enable signal? I am not getting how would it enable the specific register. Please help me out with it.

Thanks.

Answer 1

There are several inconsistencies in the diagram. The “n-to-2^n” decoder should have n inputs and 2^n outputs. With such a decoder, the number of registers should be 2^n.

The decoder inputs specify the address (i.e. the register) to be written to. For any of the 2^n possible register numbers, the corresponding output of the decoder will be set to 1, with all other outputs set to 0.

The “write” signal is probably driven off a clock.

The purpose of the AND gates is to make the “write” signal propagate to the correct register (just the one!) The register is chosen by the address fed into the decoder, as described above.

The selected register will latch onto the “register data”, most probably on the rising edge of the clock. All the remaining registers will keep their present values, since their C inputs will remain at 0 throughout.