I am trying to write this code:
for (i = 0; i <= CONST - 1'b1; i = i + 1'b1)
begin : loop_inst
if (i < 3)
begin
if (changed[i] & !done_q[i])
begin
writedata[3-i] = en[i];
writedata[2-i:0] = readdata[2-i:0];
writedata[15:4-i] = readdata[15:4-i];
end
end
else
...
Basically, the location of the bit I am trying to write to (en) changes depending on which address I am talking to, depending on i. This code is not synthesizable because i is not a constant.
Is there any other workaround to this? The only workaround I know is writing out those three statements CONST times. I am hoping I DON’T have to do that in the end. Is there any other solution?
It looks like you’re trying to copy
readdatatowritedataall the time, but fill in the LSBs withenif certain special case conditions are met. I’m also going to assume that theforloop you have is in analwaysblock, and that you’re intending to build combo logic.The
forloop as you’ve it written doesn’t make much sense to me from a hardware perspective. Aforloop is used for building arrays of logic, and as you’vewritten it you’ll have at least 3 logic cones trying to set values on the entire
writedatabus. (If it generates anything at all, it’ll be some weird priority structure).That said, it’s probably the range selects that your compiler is complaining about, ie the
writedata[2-i:0]rather than thewritedata[3-i] = en[i];(anything with:in the part select). If you want to do something along those lines, you can use ‘indexed part selects’ (+:or-:) but there are better solutions in this case.I’d rewrite it as follows – assuming I’ve assumed correctly 🙂
In this code, I’m setting
writedatatoreaddata, and then tweaking the resulting value ofwritedataif the special cases are in play. Theforloop is building 3 logic cones, one for each of the bits inwritedata[3:1]. I’d double-check if the bit mapping is what you intend -ie, mappingen[2:0]on towritedata[1:3].