I am using ModelSim in order to design and simulate CPU architectures. For those like me who know about this, you are also probably aware that it is really difficult to verify simulation data when trying to handle all those signals in front of you.
Is there a way to automatically run a simulations and perform some verification procedure in order to see if data I get are correct?
For example, I have a certain component that when stimulated by a signal, in the next clock, will return the negated signal. I want to verify this. How? (of course without manually checking signals on the screen).
Thankyou
Yes, this is known as self-checking test benches. The idea is to write a new VHDL file where you instantiate the component you want to test, apply stimuli to the component and verify the output using assertions. The basic way to do that is with the assert statement, like this:
Also try looking into PSL, which is another language for verifying behavior of VHDL code. Modelsim has support for both VHDL assertions and PSL.