I am working on a simulator for the msp430 instruction set. gnu assembler will let you encode instructions like these:
fc0a: 12 10 00 02 rrc &0x0200
fc0e: 22 11 rra #4
fc10: 23 52 add #4,#2
My guess is that rrc &0x0200 will fetch from address 0x0200 perform the rotate then write the answer back to address 0x0200, correct? But what would an rra #4 do? The source would be an immediate 4 I assume but is there a destination after the operation? The add #4,#2 assembled into what you would expect (as 2b10, source = r2, ad = 1b0, dest = r3), the binutils disassembler though did not know what to do with that instruction.
Are these valid instructions?
Although there doesn’t appears to be any definitive online reference to this effect, I tend to agree with the OP that the two instructions shown (and several others) are likely not valid, even though they conform to the format defined in the data sheets.
In other words, not all possible combinations of the various parts that make up a instruction word are valid. In particular many single operand instructions that use the immediate addressing mode, and many double operand instructions that have an immediate addressing mode for the destination are probably not semantically viable.
There are only a few hints to this effect in the documentation, for example, in the User’s Guide, section 3.3.7 (on the immediate addressing mode), a comment indicates “Valid only for a source operand.” (And, BTW, this is for all cases of immediate addressing mode, not just the short-hand cases allowed by the R2 or R3 constant generation trick.)
The fact that the disassembler doesn’t know what to do with such codes is also another hint (although… some disassemblers get tripped easily…).
For sake of documentation, I gathered below a few useful references for the MSP430: