Question

I am working on Solaris 10, Sun Studio 11. I am refactoring some old code, and trying to write unit tests for them. My make file looks like:

my_model.o:my_model.cc
    CC -c my_model.cc -I/../../include -library=stlport4 -instances=extern

unit_test: unit_test.o my_model.o symbol_dictionary.o
    CC -o unit_test unit_test.o my_model.o symbol_dictionary.o -I../../include \
    -library=stlport4 -instances=extern

unit_test.o: unit_test.cc
    CC -c unit_test.cc -I/../../include -library=stlport4 -instances=extern

symbol_dictionary.o:
    cd ../../test-fixtures && ($MAKE) symbol_dictionary.o
    mv ../../test-fixtures/symbol_dictionary.o .

In the ../../test-fixtures makefile, I have the following target:

symbol_dictionary.o:
    CC -c symbol_dictionary.cc -I/../../include -library=stlport4 -instances=extern

I do the instances=extern because I had linking problems before, and this was the recommended solution. The consequence is in each directory that is being compiled, a SunWS_Cache directory is created to store the template instances.

This is the long way to get to this question. Is it a standard practice to consolidate object files in a single directory before you link them?

Answer 1

Short answer: it is a common practice, often convenient, not always good, not always bad.

Also, your makefiles can be shorter and cleaner if you use automatic variables and pattern rules:

COMPILE = CC -I/../../include -library=stlport4 -instances=extern

%.o: %.cc
    $(COMPILE) -c $<

unit_test: unit_test.o my_model.o symbol_dictionary.o
    $(COMPILE) -o $@ $^

symbol_dictionary.o:
    cd ../../test-fixtures && ($MAKE) $@
    mv ../../test-fixtures/$@ .

in ../../test:

COMPILE = CC -I/../../include -library=stlport4 -instances=extern

symbol_dictionary.o: %.o : %.cc
    $(COMPILE) -c $<