Question

I am writing a VHDL process that needs to compare an input value to zero. The input may contain metavalues (‘U’, ‘X’, ‘L’, ‘H’, etc.), in which case zero should not be asserted.

Unfortunately, ModelSim issues a warning with each comparison:

# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 14 ns  Iteration: 1  Instance: /tb/uut

Any ideas on how to code the below in order to avoid such warnings? Turning off numeric_std warnings globally is not an option.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity Test is
    port (
        clk               : in std_logic;
        reset             : in std_logic;

        i_in_data         : in unsigned(31 downto 0);

        o_out_zero        : out std_logic
    );
end Test;

architecture rtl of Test is
begin
    process(clk, reset) begin
        if(reset='1') then
            o_out_zero <= '0';
        elsif(rising_edge(clk)) then
            if(i_in_data = (i_in_data'range=>'0')) then
                o_out_zero <= '1';
            else
                o_out_zero <= '0';
            end if;
        end if;
    end process;
end architecture;

Answer 1

If the output of o_out_zero doesn’t matter in the presence of metavalues, then the useful function to_01 from numeric_std can be used to eliminate them in the comparison expression. See also to_01xz etc for similar purposes…

Replace

if(i_in_data = (i_in_data'range=>'0')) then

with

if to_01(i_in_data) = (i_in_data'range=>'0') then

and it should be good.

You do know that parentheses around the boolean expressions in an if-statement are unnecessary, right? The less VHDL looks like C, the better…