Question

I am writing a VHDL program on quartus II for a CYCLONE III EP3C25 FPGA and I got an issue.

Here are the important part of my program:

odata : out std_logic_vector(15 downto 0);

signal buf_data : std_logic_vector(255 downto 0);

signal nb_word : integer :=0;

Process(clk,RST)
begin
    if(RST='0') then
        nb_word<=0;
    elsif(clk'event and clk='0') then
        if(Current_state_w=s2) then
            if(nb_word<=X"F0") then
                nb_word<=nb_word+16;
            else
                nb_word<=0;
            end if;
        end if;
    end if;
end process;

Process(clk,RST)

begin
    if(RST='0') then
        odata<=(OTHERS=>'0');
    elsif(clk'event and clk='0') then
            odata<=buf_data(nb_word+15 downto nb_word);
    end if;
end process;

This code is compiling fine but does not do what I want then I just wanted to change :

odata<=buf_data(nb_word+15 downto nb_word);

in

odata<=buf_data(nb_word downto nb_word-15);

And I changed the initialisation and reset value of nb_word at 15 instead of 0.

The problem is, when I do that and I try compiling I got this error:

Error (10779): VHDL error at VL_control.vhd(99): expression is not constant

The line corresponds to the changement of the odata line.

I really can’t understand why I got this error. Why is it possible to do an addition and not a substraction?
I also tried to define another signal and to do the substraction in the signal before addressing the buffer like that:

nb_word1 := (nb_word-15);
odata<=buf_data(nb_word downto nb_word1);

But I still get the same error. Where does that come from?????

Answer 1

You should limit nb_word to an integer range, that way the sythesis tool knows for sure that the value of nb_word - 15 can not be negative.

Also, why do you compare an integer to a bit string literal? Why not just say if nb_word < 15?