I can’t imagine an architecture would design an access to its smallest data type in multiple instructions, but maybe there is some problem with pipelining that I am not considering?
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I can’t imagine an architecture would design an access to its smallest data type in multiple instructions, but maybe there is some problem with pipelining that I am not considering?
Whether a
boolobject is read and written in a single operation is not guaranteed by the C++ standard, because that would put constraints on the underlying hardware, which C and C++ try to minimize.However, note that in multi-threading scenarios the question whether reading/writing a data type is atomic is only one half of the problem. The other half is whether changes to some address are reflected in all caches (i.e. those local to different cores), and whether they are reflected across all threads in the same order. For that you will need memory barriers.