Question

I got WebPack up and running on my machine again and after synthesizing a simple design and uploading it to my FPGA, I encountered quite a problem with my understanding.

When there is a line like this in the user constraint file:

NET "W1A<0>" LOC = "P18" ;

How exactly does the synthesis software determine how this pin gets assigned to by the VHDL code?

For instance, take this example code I’ve been provided with:

entity Webpack_Quickstart is
Port (
W1A : out  STD_LOGIC_VECTOR(15 downto 0);
rx : in STD_LOGIC;
tx : inout STD_LOGIC;
clk : in STD_LOGIC
);
end Webpack_Quickstart;

architecture Behavioral of Webpack_Quickstart is
signal counter : STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
begin
    W1A(0) <= '1';
end;

How exactly does this code make the WIA0 pin on my FPGA turn on? What is the link? Is it just the name of the port in the entity declaration is there more magic involved?

Answer 1

Your .ucf constraints are applied in the implementation phase. At this point your design has been synthesized, and the available top-level nets are thus “known”. So yes, it is only a matter of matching equally named nets to equally named constraints.

The syntax is slightly different though (using <> instead of () for indexing vectors for instance), but otherwise it’s just a simple string match.

The easiest way to initially configure your pin constraints, especially for large designs, is to just use one of the graphical tools (PlanAhead, if it’s included in the WebPack) to assign the pins, and generate an initial .ucf file.
I find that making small changes later on is easiest to do by hand using the standard ISE text editor directly though.