Question

I have a basic question about the policy followed by the memory system.

Consider a core with private L1 and L2 caches. After L2 cache we have a bus on which the coherence traffic runs. Now, if a cache line for address(X) is evicted from the L2 cache, is it necessary to evict that address from the L1 cache ??

The reason for eviction can be that it helps in maintaining the invariant of the coherence protocol [if a line in l2 shows invalid this core does not contain this address].

Answer 1

There are three different designs and all are used.

1. Exclusive: Data in the L1 cache is never in the L2 cache. Data in the L2 cache is never in the L1 cache.

2. Inclusive: Data in the L1 cache must also be in the L2 cache.

3. Neither: Data in the L1 cache may or may not be in the L2 cache.

Each of these has advantages and disadvantages. The inclusive scheme allows the cache coherency protocol to ignore the L1 cache — if data isn’t in the L2 cache, it isn’t in the L1 cache. But the exclusive scheme makes the most effective use of precious cache memory.

Inclusive designs are becoming more popular because faster inter-core synchronization is becoming more important than having slightly larger effective cache sizes.