Question

I have a directory in which I keep adding different C++ source files, and generic Makefile to compile them. This is the content of the Makefile:

.PHONY: all clean

CXXFLAGS = -pipe -Wall -Wextra -Weffc++ -pedantic -ggdb

SRCS = $(wildcard *.cxx)
OBJS = $(patsubst %.cxx,%.out,$(SRCS))

all: $(OBJS)

clean:
    rm -fv $(OBJS)

%.out: %.cxx
    $(CXX) $(CXXFLAGS) $^ -o $@

NOTE: As is obvious from above, I am using *.out for executable file extensions (and not for object file).

Also, there are some files which are compiled together:

g++ file_main.cxx file.cxx -o file_main.out

To compile such files, until now I have been adding explicit rules in the Makefile:

file_main.out: file_main.cxx file.cxx

file.out: file_main.out
    @echo "Skipping $@"

But now my Makefile has a lot of explicit rules, and I would like to replace them with a simpler implicit rule.

Any idea how to do it?

Answer 1

First, this method of compiling several source files directly into an executable is not a terribly good idea. The more common compile-then-link approach will save a lot of unnecessary compilation.

That said, the way to replace many explicit rules with a simpler rule depends on what the explicit rules have in common. You already have a pattern rule:

%.out: %.cxx
    $(CXX) $(CXXFLAGS) $^ -o $@

and if all you want to do is add another source file to a particular target, you don’t have to do this:

g++ file_main.cxx file.cxx -o file_main.out

you can get the effect just by adding a prerequisite (in a line by itself):

file_main.out: file.cxx

If you have several targets with that pattern, you can use a pattern rule:

file_main.out another_main.out a_third_main.out: %_main.out : %.cxx

If you have many such targets, you can use a variable:

MAIN_THINGS = file another a_third a_fourth and_yet_another
MAIN_TARGETS = $(addsuffix _main.out, $(MAIN_THINGS))
$(MAIN_TARGETS): %_main.out : %.cxx

And you can add other patterns for other target sets, even overlapping sets. Does that cover your situation?